1. Field of the Invention
This invention relates to semiconductor packaging technology, and more particularly, to a solder-bump fabrication method for fabricating solder bumps with high coplanarity over a semiconductor chip for flip-chip application.
2. Description of Related Art
The flip-chip technology is an advanced semiconductor fabrication technology that allows the overall package size to be made very compact. The flip-chip package configuration differs from conventional ones particularly in that it mounts the semiconductor chip in an upside-down manner over the chip carrier and electrically coupled to the same by means of solder bumps provided on the active surface of the semiconductor chip. Since no bonding wires are required, which would otherwise occupy much layout space, the overall size of the flip-chip package can be made very compact as compared to conventional types of semi-conductor device packages.
The attachment of solder bumps to a flip chip requires the provision of the so-called UBM (Under Bump Metallization) pads on the active surface of the semiconductor chip, which is wettable to the solder bumps so that the solder bumps can be securely attached to the flip chip. After the UBM structure is formed, a solder-bump fabrication process is performed to form a solder bump on each UBM pad. Conventionally, there are various techniques that can be used to implement the solder-bump fabrication process, including, for example, electroplating, screen printing, evaporation, and so on. One example of the utilization of electroplating technique for solder-bump fabrication is illustratively depicted in the following with reference to FIGS. 1A-1E.
Referring to FIG. 1A, in the flip-chip fabrication, the first step is to prepare a semi-conductor chip 100 having a plurality of bonding pads (only two are shown in FIG. 1A, respectively designated by the reference numerals 101, 102). Further, a passivation layer 110 is formed over the active surface of the semiconductor chip 100, and which is selectively removed to expose the bonding pads 101, 102. Next, an array of UBM pads (only two are shown in FIG. 1A, respectively designated by the reference numerals 121, 122) are formed respectively over the bonding pads 101, 102.
Referring further to FIG. 1B, the next step is to perform a solder-bump fabrication process, in which a mask 130, such as a dry-film mask, is first disposed over the passivation layer 110. The mask 130 is predefined with a plurality of openings (only two are shown in FIG. 2B, respectively designated by the reference numerals 131, 132) to exposed the UBM pads 121, 122.
Referring further to FIG. 1C, in the next step, a solder-electroplating process is performed to electroplate a selected solder material, such as Sn/Pb (tin/lead) alloy, through the mask openings 131, 132 onto the UBM pads 121, 122. As a result of this process, a first solder bump 141 is formed over the first UBM pad 121, while a second solder bump 142 is formed over the second UBM pad 122.
During the foregoing solder-electroplating process, however, the electroplating electrical current applied to the UBM pads 121, 122 may be undesirably inconsistent in amounts. Moreover, the electrolyte being used in the solder-electroplating process may be undesirably subjected to disturbances. These two factors would cause the resulted solder bumps 141, 142 to be formed with different volumes.
Assume the first UBM pad 121 receives a smaller amount of electroplating electrical current, whereas the second UBM pad 122 receives a larger amount of electroplating electrical current during the solder-electroplating process. In this case, the electroplating of solder over the second UBM pad 122 would be faster in rate than that over the first UBM pad 121. Consequently, as illustrated in FIG. 1C, as the solder-electroplating process is completed, the second solder bump 142 formed over the second UBM pad 122 would be larger in volume than the first solder bump 141 formed over the first UBM pad 121.
Moreover, the electroplated solder would extend beyond the topmost surface of the dry-film mask 130 and spread horizontally over the dry-film mask 130, rendering the resulted solder bumps 141, 142 into a mushroom-like shape that may likely make the neighboring solder bumps 141, 142 bridged to each other. If bridging occurs, the solder bumps 141, 142 would be nevertheless jointed together after reflow, making them short-circuited to each other.
Referring further to FIG. 1D, in the next step, the dry-film mask 130 is removed, leaving the first solder bump 141 over the first UBM pad 121 and the second solder bump 142 over the second UBM pad 122.
Referring further to FIG. 1E, in the next step, a solder-reflow process is performed to reflow the mushroom-like solder bumps 141, 142. After reflow, the solder bumps 141, 142 which become more rounded in shape.
However, as mentioned earlier, the second solder bump 142 formed over the second UBM pad 122 is larger in volume than the first solder bump 141 formed over the first UBM pad 121 due to a larger electroplating electrical current being applied to the second solder bump 142 and a smaller electroplating electrical current being applied to the first solder bump 141 during the solder-electroplating process. This would undesirably make the reflowed second solder bump 142 to be greater in height than the reflowed first solder bump 141, with a height difference of xcex94H, which is typically 100 xcexcmxc2x110 xcexcm (micrometer), as illustrated in FIG. 1E. In other words, the resulted solder bumps 141, 142 would have poor coplanarity. The non-coplanarity in bump height would undesirably make the resulted flip-chip package distorted in construction.
One solution to the foregoing problem is disclosed in U.S. Pat. No. 5,536,677 entitled xe2x80x9cMETHOD OF FORMING CONDUCTIVE BUMPS ON A SEMICONDUCTOR DEVICE USING A DOUBLE MASK STRUCTURExe2x80x9d, which is characterized in the use of a double mask structure to help allow the resulted solder bumps to have substantially the same volume and height for high coplanarity. One drawback to this patented technology, however, is that the use of double mask structure would make the overall fabrication considerably more complex to implement.
It is therefore an objective of this invention to provide a solder-bump fabrication method, which can help allow the fabricated solder bumps to have high coplanarity.
It is another objection of this invention to provide a solder-bump fabrication method, which can help allow the fabricated solder bump not to have a mushroom-like shape for prevention of short-circuiting between neighboring solder bumps.
In accordance with the foregoing and other objectives, the invention proposes a new solder-bump fabrication method.
Broadly defined, the solder-bump fabrication method of the invention comprises the following procedural steps: (1) forming an array of UBM pads over the semiconductor chip; (2) forming a mask over the semiconductor chip, the mask being predefined with a plurality of openings to expose the UBM pads; (3) performing a solder-electroplating process to electroplate a solder material through the mask openings onto the UBM pads until the topmost surface of the electroplated solder over the UBM pads reaches a predefined height below the topmost surface of the mask to thereby form an electroplated solder layer over each of the UBM pads; and (4) performing a screen-printing process to fill solder paste into the remaining void portions in each of the mask openings to thereby form a printed solder layer over each electroplated solder layer.
The foregoing solder-bump fabrication method is characterized in the use of a two-step solder-bump fabrication process, including a first step of electroplating solder over UBM pads to a controlled height still below the topmost surface of the dry-film mask, and a second step of screen-printing solder paste over the electroplated solder layer. Compared to the prior art, since the solder-bump fabrication method of the invention allows the solder material electroplated and printed over the UBM pads to be confined within the mask openings and never exceed the topmost surface of the mask, the resulted solder bumps would not be bridged to neighboring ones. Moreover, the solder-bump fabrication method of the invention allows all the resulted solder bumps to be substantially equally sized to achieve high coplanarity.